Quantitative characterization of the trapped charge profile in GaN HEMTs by sense nodes in the drain-extension region

A new methodology is presented that directly extracts the location and amount of trapped charge in GaN HEMTs by making use of a special test structure with an additional sense node in-between the gate and drain. The technique is validated on three wafer types: one for which trapping predominantly occurs in the GaN epitaxy, one with both epitaxy trapping and surface charge injection, and one for our optimized 650-V GaN technology, for which charge trapping is almost completely eliminated.