A Verilog-A model of a charge sensitive amplifier for a HV-CMOS pixel sensor

The use of hybrid pixel detectors in High Energy Physics (HEP) have allowed particle tracking reconstruction with an unprecedented precision. These detectors are expensive to assembly and the bump size limits the minimum pixel size. In order to overcome those limitations full monolithic pixels are being investigated. The idea is to integrate into the same chip the sensor matrix and the readout electronics. Simultaneously, new methods for measuring the energy of the detected particles with higher precision that those achievable by using the Time Over Threshold (TOT) technique are under study. This paper presents a behavioral model of the preamplifier stage of a pixel readout channel written in Verilog-A. The purpose of this model is to allow studying different solutions for measuring the energy with higher precision without the need to design the readout channel at transistor level. The presented model is very simple and written as a function of the main parameters of the pre-amplifier stage, that is, open loop gain, bandwidth, coupling capacitor, and feedback capacitor.