An optimization-based design methodology with PVT analysis for ultra-low voltage analog ICs

This paper presents a design methodology for ultra-low voltage (ULV) analog integrated circuits. This methodology is based on an optimization process using Simulated Annealing (SA) heuristic and electrical simulations. The SA algorithm explores the design space to obtain design feasible solutions at the same time that the effects of process, voltage and temperature (PVT) variations are analyzed with corners simulations. A low-pass filter was designed in the TSMC 130 nm process using the proposed methodology. The results show a 0.5-0.6 V active filter with 2.47 MHz cut-off frequency and power dissipation of 640 μW, in according with the IEEE 802.15.4 standard for 2.5 GHz low power receivers.