An 8bit logarithmic AD converter Using cross-coupled inverters and a time-to-digital converter

This paper presents an 8bit logarithmic AD converter comprising two conversion elements. One of the elements is a time-to-digital converter with a linear transfer characteristic and another is a voltage-to-time converter with a logarithmic transfer characteristic comprising two cross-coupled inverters. Simulation results for transistor level and post layout extraction are presented and discussed for an implementation in the UMC 130nm technology. Transistor level simulation results agree well with the theoretical prediction and post layout simulation results closely following the transistor level simulation results.