A fully synthesized key establishment core based on tree parity machines in 65nm CMOS

This paper presents a low-area ASIC implementation of a fully-synthesized symmetric key establishment architecture based on tree parity machines (TPMs) in 130nm and 65nm standard-cell CMOS technologies. The proposed circuit architecture has a serial datapath with re-keying characteristic enabled by a proposed pseudo-random binary sequence (PRBS) generator based on variable-length linear-feedback shift register (LFSR). A circuit technique is proposed that enhances datapath access to add re-keying feature. Fully-synthesized results for 130nm and 65nm show an area consumption of 0.016mm
²
and 4800μm
²
respectively. Relative area and power consumption are studied by comparing synthesized TPMs with an implementation of a CRC16 error detection code used within security applications. Comparison is made through a proposed figure of merit that include the generated key length in order to show scalability of the architecture with the available technologies.