Advanced circuit interface for systems with multiple voltage domains

Multi-level voltage scaling is a highly effective technique for reducing power and matching required speed in an integrated circuit. However, additional circuitry is required at the interfaces of the circuit blocks which operate at different voltage levels. These circuits impose a significant delay overhead and can prohibit the use of multi-voltage scaling at specific critical paths. These paths often cross boundaries of blocks that can otherwise operate at a different supply voltage, eliminating the benefits of multiple voltage domains. A by-pass circuit is proposed to alleviate these timing issues and simultaneously support multi-voltage scaling under specific operating conditions. The new circuit results in performance improvements of up to 89% and power reduction up to 52% compared to traditional level-up and level-down shifters in a 32 nm technology node. Furthermore, greater performance and power savings are demonstrated where more cells are being by-passed, such as the isolation cells.