Boiling sensitivity analysis of asymmetrically heated micro-scale devices

Thermal challenges in 3D ICs have driven the need for embedded chip cooling. In this paper, we measured the thermal performance of a two-phase system employing flow boiling in chip-embedded micro-channels utilizing the latent heat of vaporization of dielectric refrigerants (such as R-1234ze) In the present study, an investigation was performed on a 20 mm × 20 mm thermal test vehicle having a heater layer to simulate the heat generation from a state-of-the-art 8-core microprocessor chip and a sensor layer to measure temperature at key locations within the test vehicle. Fluidic channels in the form of radial expanding micro-scale cavities with micro-pin fields were etched into the test vehicle. The micro-pin fields represent the through-silicon-via (TSV) interconnects present in multi-die stacks. The heaters are used to simulate a background heat flux of 20 W/cm2 and individual core heat fluxes of up to 210 W/cm2. This heat generation capability corresponds anywhere from a processor low-power idle mode to a high-power super-turbo mode and beyond. Since the flow resistance in a microchannel for two-phase cooling depends on in-situ heat generation, asymmetric power dissipation due to different power levels in various cores and non-core areas may unbalance the overall flow distribution. Furthermore, it may reduce the local heat transfer rate and even lead to premature failure of working cores. This study aims at understanding the effects of asymmetric heat flux profiles on flow resistance and boiling heat transfer.