Universal Charge-Conserving TFET SPICE Model Incorporating Gate Current and Noise

An analytical compact model for tunnel field-effect transistor (TFET) circuit simulation is extended by adding a gate tunnel current model, a charge-based capacitor model, and a noise model. The equation set is broadly applicable across materials systems and TFET geometries and is readily fitted to rigorous physics-based device simulations and experimental results. To validate the gate current and charge models, technology computer-aided design (TCAD) simulations of a GaN/InN/GaN TFET are used. TCAD simulations show that the gate tunneling current depends on the gate-drain bias with a 100%/0% drain/source current partition. Terminal capacitances evaluated from the charge model agree well with simulations. The model is implemented in Verilog-A and the significance of gate current in the circuit design is illustrated in an amplifier design.