A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network

In this paper, a 1.5-GS/s 5-bit interpolating analog-to-digital converter (ADC) with offset averaging and interpolating sharing resistors network (OAISRN) is presented. The proposed OAISRN is based on conventional flash ADC and the concept of zero crossing points in folding and interpolating architecture. In order to reduce power dissipation yet to make a high performance, it removes half of preamplifiers and ensures matching by using offset averaging and 2x-interpolation sharing resistors network behind the initial zero crossing points generators array. Implementation of the OAISRN is explained in detail and its impact on signal bandwidth is discussed. The interpolating ADC in TSMC 65 nm process achieves SNDR of 27.8 dB and SFDR of 37.7 dB for 745 MHz input frequency located at 1.5 GS/s in postsimulation. The power consumption is 9.6 mW under a supply voltage of 1.2 V.