A 100MS/s 5bit fully digital flash ADC with standard cells

A 5bit fully digital Flash ADC is presented. It's featured with time delay comparators with embedded differential reference. In this design, differential input analog signals are converted to time delays by a pair of voltage to time converters and the two delay signals are eventually latched to acquire corresponding digital code. No reference from outside is needed. By using standard cells from the digital library, this flash ADC is improved a lot in power, area and design complexity compared to conventional mixed signal ADC. It consumes 587μW and achieves an SFDR of 37.9dB, SNDR of 29.1dB under sampling rate of 100MS/s by post simulation, with a FOM of 240fJ/conversion-step.