Evaluation of power efficient modified convolution coder and maximum likelihood decoder for wireless communication systems

In this paper, by modifying traditional convolution coder and maximum likelihood decoder based on trellis decoding, a very power efficient coder and decoder is proposed which is compatible for wireless communication system. The hardware implementation of the modified convolution coder and corresponding maximum likelihood decoder is very simple which minimizes complex circuit involvement thus reducing overall power consumption drastically. The coder and decoder design is based on Agilent Technologies `System Vue' EDA tools and the hardware implementation is on Xilinx Spartarn-6 FPGA board. In this coding technique transmitted codes are chosen selectively from the set of all possible codes generated for constraint length= 9 to increase the hamming distance between the codes which helps to decrease BER. The Coder and Decoder blocks are tested both in simulation and hardware environment by feeding baseband and coded data. The simulation result obtained is very encouraging. Perfect decoding of the baseband data are obtained with very low BER, low Power and low latency.