ESD reliability improvement of the 0.25-µm 60-V power nLDMOS with discrete embedded SCRs separated by STI structures

In this paper, the electrostatic-discharge (ESD) robustness improvement by modulating the drain-side embedded SCR of an HV nLDMOS device is investigated via a TSMC 0.25 µm 60 V process. After a systematic layout design and data analysis, it can be found that the holding voltage (Vh) of an nLDMOS with a parasitic SCR “npn”-arranged type & thin oxide (OD) discrete (i.e. separated by the shallow-trench isolation (STI) structure) distribution in the drain-side have greatly increased with the parasitic SCR OD decreasing. Therefore, a high Vh value in the OD discrete parameter 2 (DIS-2) can be obtained about 13.3 V. On the other hand, the trigger voltage (Vt1) values and the holding voltage (Vh) values of the nLDMOS DUTs with a parasitic SCR “pnp”-arranged type & OD discrete distribution in the drain-side are slowly increased with the parasitic-SCR OD decreasing. The best Vh value in the “pnp”-arranged type & OD discrete parameter 2 (DIS-2) is about 14.4 V. Meanwhile, the secondary breakdown current (It2) values of this type are greater than 7 A except for the OD discrete parameter 2 and 3. Therefore, an appropriate layout of nLDMOS embedded with a drain-side “pnp” arranged type & OD discrete distribution that can yield high ESD and latch-up (LU) robustness levels.