Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors

A framework is proposed to perform timing analysis of state-of-art microprocessors considering the impact of process-voltage-temperature (PVT) variations and the aging effect, including bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). In this work, not only statistical timing analysis (StTA) due to each wearout mechanism is studied individually, but also the performance degradation while all these wearout mechanisms happen simultaneously is analyzed. Moreover, this work takes into account realistic use scenarios which include active, standby, and sleep modes. A unified gate-delay model, which combines both PVT variations and the aging effect, is constructed via a technique called multivariate adaptive regression splines (MARSP). Then a timing engine, which consists of two parts: a block-based analyzer and a path-based analyzer, is built to perform PVT-reliability-aware timing analysis. The accuracy and effectiveness of our framework has been verified on large industrial designs, like the LEON3 microprocessor, through a comparison with SPICE.