The Cu exposure effect in AIO etch at advanced CMOS technologies

In advanced CMOS technology nodes with Cu/low-k interconnect, metal hard-mask approach AIO etch is the key process to define the physical structure of Cu line and via. The via hole and via slot always land on lower metal Cu as design rule requested. The time of beneath Cu exposed to fluorocarbon plasma in etch stop layer (ESL) opening step, especially for the via slot area, is critical for final trench depth and residual defect formation. The mechanism and solution of this phenomenon are addressed.