Impact of across-wafer variation on the electrical performance of TSVs

A simulation methodology is presented by which measured equipment variation during silicon DRIE is quantified and the effective variation in the electrical performance of the final TSV devices is found. Using the level set method, process simulations are performed in order to generate structures representative of the equipment variation. The across-wafer variation of the resulting scallop geometry is about 20%, while the electrical performance, including the resistance, capacitance, and inductance of the devices was found to not vary beyond 1%.