3D die level packaging for hybrid systems

The aim of this work is to develop and optimize processing technologies required for 3-D die level packaging of hybrid systems including MEMS and MOS components. In this paper we report the process development for stacking of ultra-thin silicon dies (as low as 10 μm) and a basic 5 μm thick MEMS device (Cantilever). SU-8 has been used as the patternable dielectric filler between the device layers.