Design-for-stress for CMOS technologies - the next frontier

Summary form only given. Sources of the stress effects in CMOS technologies are summarized, and an overview of the recent trends is given. The consequent emergence of mechanical stress related effects on yield, functionality and/or performance of CMOS IC's is outlined. Based on these trends it is concluded that the mechanical stress effects must be addressed, and managed through the architecture and design of the IC's. Some of the challenges in addressing the underlying interactions are highlighted, and several opportunities for solving the problems are identified. A possible path towards a practical solution and implementation is proposed, based on historical precedents and typical industry practices.