Integrating open TCP/IP core and FPGA-based cryptosystem on chip

Ensuring network traffic privacy and improved performance is a key factor to provide trustworthy communication for data transmission. In this research work, we investigate a mechanism to integrate our previous works: open TCP/IP core and the cryptosystem on the same Field-Programmable Gate Array (FPGA) chip. Challenges are addressed in this paper regarding the data format of the encrypted message and the method to handle this format by open TCP/IP core. In addition, both integrated systems (TCP/IP and cryptosystem) exhibit different throughput measurements. Thus, a buffer systems is proposed to mitigate the throughput variance. Analysis of total interfacing time delay is evaluated accordingly.