Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces

Many embedded applications process large amounts of data using regular computational kernels, amenable to acceleration by specialized hardware coprocessors. To reduce the significant design effort, the dedicated hardware may be automatically generated, usually starting from the application’s source or binary code. This paper presents a moduloscheduled loop accelerator capable of executing multiple loops and a supporting toolchain. A generation/scheduling procedure, which fully relies on MicroBlaze instruction traces, produces accelerator instances, customized in terms of functional units and interconnections. The accelerators support integer and single-precision floating-point arithmetic, and exploit instruction-level parallelism, loop pipelining, and memory access parallelism via two read/write ports. A complete implementation of the proposed architecture is evaluated in a Virtex-7 device. Augmenting a MicroBlaze processor with a tailored accelerator achieves a geometric mean speedup, over software-only execution, of 6.61
$\times $
for 13 floating-point kernels from the Livermore Loops set, and of 4.08
$\times $
for 11 integer kernels from Texas Instruments’ IMGLIB. The proposed customized accelerators are compared with ALU-based ones. The average specialized accelerator requires only 0.47
$\times $
the number of field-programmable gate array slices of an accelerator with four ALUs. A geometric mean speedup of 1.78
$\times $
over a four-issue very long instruction word (without floating-point support) was obtained for the integer kernels.