Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region

A near-threshold voltage (NTV) operation provides a recognized approach to low-power circuit design due to its balancing of minor performance degradation relative to its significant power savings. However, the scaling voltage and the technology process give rise to increased susceptibility to radiation-induced soft errors for systems operating at NTV. In this brief, we develop new results for the evaluation of alternatives to mask single-event transients in combinational logic and single-event upsets in storage elements for three commonly utilized redundancy approaches, namely, spatial, temporal, and a hybrid of both spatial and temporal. The performance and energy impact of each approach is quantified at the NTV operation. Additionally, the impact of an increased effect of threshold voltage variation at NTV is assessed for all redundant systems. We also investigate the effect of technology scaling by comparing the energy and performance variation of the 45-nm MOSFET planar and the 16-nm high-κ/metal-gate bulk fin-typed field-effect transistor structures as modeled by the Predictive Technology Model NanGate open source library via simulations in HSPICE. The results indicate that delay variation of temporal redundancy (22.34%) is lower than the variation of both triple module redundancy and selfvoting dual module redundancy (31.6% and 35.2%, respectively), although the variation of 16-nm is beneath that of 45-nm technology node for both. On average, operating at NTV using trigate 16-nm bulk FinFET devices reduces energy consumption and incurs less performance impact for redundant systems. Utilizing temporal redundancy based on a trigate 16-nm process achieves 56.2% energy savings at a 27.6% delay increase compared with a spatial redundancy approach.