Low power issues in a digital programmable artificial retina

Programmable Artificial Retina (PAR) means lodging a digital processing element in each pixel of a focal plane array. A PAR is faced with constraints coming from the meeting of both optical sensor and processor domains. Since image sensing is sensitive to device temperature, heat dissipation should be limited. A high resolution sensor implies a large chip and small pixel area. Combining these characteristics with the power hungry nature of the vision processing task ends the equation to be consider. Large array means many processors and potentially power consumption without the usual possibility of trading power against silicon area, due to extreme geometrical constraints. The considerations therein are based on experimenting with our last PAR chip fabricated in standard 0.8 /spl mu/m CMOS technology, called PVLSAR2.2, which features a resolution of 128/spl times/128 pixels and among other features, the ability to operate both under and above threshold voltage. Power considerations are tackled at three levels: power savings from the artificial retina concept at the vision system level, power issues from the global architecture of the chip and reducing power consumption in the processing task itself.