Comparative performance analysis of single stage differential amplifier at 32 nanometer regime

The MOSFET scaling approaches on the road to limitations alternatives are upcoming, to overcome these limitations. This paper deals with the design of single stage differential amplifier featuring 32nm gate length. Due to the shrunken size of devices, it inhabits less die-area. There are various Nano devices such as CNFET and FinFET. In this paper, we begin to talk over the role of MOSFET, FinFET and CNFET in the design of single stage differential amplifier and its contribution towards Gain, CMRR, Slew Rate and power consumption. The proposed conventional single stage differential amplifier using FinFET yields an open loop Gain 18.5 dB, Slew Rate 19.2E+06 V/μsec, CMRR 11.34 dB the circuit is operated at 1.8 V using Hspice simulation software. The simulations best part is that, at the existing stage of the technology scaling, the FinFET circuit seems to perform best than the MOSFET and CNFET at the cost of power consumption.