A 2D Proof of Principle Towards a 3D Digital SiPM in HV CMOS With Low Output Capacitance

The 3D vertical integration of SPAD and readout electronics is a promising avenue to high performance photodetectors. This approach will minimize most limitations of current SiPM and lead to better performances in terms of effective PDE, timing and added functionalities. In this paper, we present a new integrated digital SiPM electronic architecture. This specific architecture aims to replace conventional analog SiPM with the added benefits of a significantly lower and constant output capacitance as well as immunity to SPAD to SPAD gain variation on the single photon resolution while providing an analog-like output signal waveform representing the sum of all triggered SPADs. This electronic architecture also offers options to turn off noisy SPADs, to reduce afterpulsing through a programmable hold-off time and to adjust the dynamic range of the output depending on the photon flux. While the 3D integration process development is underway, we realized a 2D version as a proof of principle of the electronic architecture. The 2D detector presented in this article is composed of an array of 242 pixels for a size of 1.1 × 1.1 mm
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. The output capacitance of the device is 5.6 pF/mm
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, the timing jitter associated to the quenching circuit is about 40 ps FWHM and the maximum timing skew within the array is about 70 ps, which could still be optimized.