Power delivery impedance impact of power gating schemes

Optimal power performance balance is critical for high performance microprocessors. This paper addresses different microprocessor power gating architectures and their impact to power performance trade-offs considering AC and DC metrics. It is shown that package resource allocation is critical to ensuring effectiveness of expensive die capacitance used for mitigating voltage droop. Power delivery impedance including the effect of power gating architecture and package resources is analyzed in detail to provide design guidelines. Experimental data from Intel® VI generation Core™ processor is presented for validation.