An efficient soft decision reed-solomon decoder for moderate throughput

Soft decision decoding for Reed-Solomon codes has been proven to provide large coding gains in comparison to conventional hard decision decoding. Out of the numerous soft decoding algorithms, information set decoding has turned out to be an efficient approach, if coding gains larger than 0.5 dB are desired for the widely used RS(255,239) code. In this paper we investigate new hardware implementations for information set decoding for moderate throughput applications with the aim to reduce the decoder area. We propose new efficient architectures for the key components, i.e. LLR sorting, Gaussian elimination and parity check matrix storage. The decoder requires 4950 lookup tables and 5340 flipflops on a Virtex 5 FPGA to achieve 0.7 dB gain over hard decision decoding. This is approximately 3 to 20 times less FPGA resources than other state-of-the-art architectures with similar coding gain at the expense of throughput. The decoder throughput fulfils the requirement for many applications with moderate demands, like DAB or DRM.