Theoretical Analysis of Planar Flat Floating Gate NAND Flash Device and Experimental Study of Floating-Gate (FG) / Charge-Trapping (CT) Fusion Device for Comprehensive Understanding of Charge Storage and Operation Principle

The planar flat FG device is theoretically studied extensively. There is a puzzle whether the charge is stored in the inter gate dielectric (IGD). A planar cell has no geometrical coupling ratio help thus IGD bears very high E-field. A high work function FG together with a robust interfacial layer between FG and high-K material that has both large barrier height and large dielectric constant are needed to reduce the out tunneling current. Thus our detailed tunneling simulation indicates that to obtain an “ideal planar FG” device with a large memory window but without charge-trapping in IGD is quite challenging. On the other hand, a very interesting finding from our simulation is that the opposite scenario assuming charge trapping in IGD can also provide identical ISPP/ISPE characteristic as the ideal FG device. This leads to a paradox (Rashomon) for a correct theoretical model for the device. In order to solve this paradox, we propose to apply a gate-sensing and channel-sensing (GSCS) technique to detect the charge location and dig out the real answer of operation principle. GSCS study of FG SONOS “Fusion” device shows that in a device that has both FG and trapping IGD the FG holds only limited amount of electrons and most electrons are stored in the IGD. Finally, the FG/CT fusion devices of the planar FG SONOS and FG BE-SONOS (without high-K and metal gate) are experimentally studied. They show very large memory window (>16V) with nearly ideal ISPP/ISPE slope ~1.