Novel multi-Gbps bit-flipping decoders for punctured LDPC codes

Conventional bit-flipping (BF) algorithms spectacularly fail to handle punctured LDPC codes as they use hard decisions and, therefore, they cannot effectively cope with zero-reliability punctured symbols. However, BF techniques lead to low-cost high-speed decoders. This paper introduces a novel method that enables the use of BF-based iterative decoders for punctured LDPC codes. An erasure preprocessor is introduced and is shown to successfully mitigate the impact of puncturing, substantially improving the coding gain achieved for punctured codes under BF decoding. The proposed technique renders BF decoding of punctured codes useful, something that was not possible so far to our knowledge. Furthermore, two hardware architectures are introduced and evaluated. Hardware sharing is shown to efficiently exploit common structures in the proposed combined erasure and BF decoder, leading to a new architecture found to be particularly efficient. The proposed architecture requires extremely low hardware resources, facilitating full-parallel architectures that sustain multi-Gbps throughput rates when implemented on Virtex-7 FPGA devices.