Process variation-aware approximation for efficient timing management of digital circuits

With the ever decreasing transistor feature size in recent years, process variation has become a serious challenge in digital system design, mainly due to the undesirable timing uncertainty it introduces in circuits. This variation in the size of circuit components changes the logic and wire delays that in turn, may result in delay faults or clock degradation. In this paper, we propose to use the emerging approximate computing technique to tackle the process variation problem in new technology points. In this method, functional units (sub-blocks) along critical paths are replaced with a faster approximate version to guarantee timing closure in presence of process variation. Approximation not only applies to critical path sub-blocks but also to the paths with the length close enough to critical path length that variation can potentially increase their delay over the critical path. Evaluation results under several benchmarks show that this method can give a required safety margin against delay faults, while its side-effect, i.e. accuracy loss, is still low and acceptable.