FPGA based hardware implementation of adaptive equalizer for Rayleigh fading channel

In this paper a novel approach is made to design a real-time adaptive equalizer based on Least Mean Square (LMS) adaptive algorithms in hardware domain. The FPGA platform is used to model the digital circuitry of the equalizer. A new and simple technique known as "Hardware Co-simulation" is used to configure XC6SLX45 FPGA board. In the initial phase of designing, additive white Gaussian noise (AWGN) channel is used to add noise. In the second phase Rayleigh fading channel is used since the wireless transmission scenario resembles the Rayleigh fading channel. Digital circuitry for AWGN channel requires only real valued computation whereas Rayleigh channel requires complex valued computation. According to the literature survey, limited research work has been done in hardware domain on adaptive equalizer. Therefore the objective of this work is to implement adaptive equalizer in FPGA platform and have a realtime analysis of the equalizer in the hardware domain.