Identification of delay defects on embedded paths using one current sensor

This paper is focused on developing an ATPG-based method that is orthogonal to existing post-silicon debug methods for delay defects. Given an embedded path that contains a small number of gates, the proposed ATPG generates two test vectors so that a current sensor can measure its delay with high accuracy. Unless the cumulative defect along the path is very small, the proposed method will either determine that all locations on it are fault-free or some are defective. This will benefit post-silicon debug methods and, ultimately, failure analysis. No modifications are required in the circuit layout and the routing of the power lines. Experimental results on some of the largest ISCAS85, ISCAS89 and ITC99 benchmarks show that the proposed ATPG tool is capable of generating test vectors which measure the delay of embedded paths that cover on average approximately one fourth of the gates. These results indicate the promise of the method.