FPGA-controlled PCBA power-on self-test using processor's debug features

When facing in-field board test, the functional approach plays an important role. Often, it corresponds to forcing the processor to execute a test program (which could be an application one), observing the produced results (e.g., by looking at the results written in the memory at the end of the test program execution). However, the fault coverage that can be achieved in this way is often difficult to compute, and limited by the reduced observability. In this paper we propose to use the debug features provided by many processors to enhance the observability, and hence the achieved fault coverage. In the proposed architecture we monitor on-the-fly during the test program execution the information accessible through the debug port using an ad hoc module mapped on an FPGA which is assumed to exist close to the processor. We provide experimental results showing the feasibility and cost of the approach, and demonstrate that it can provide a significant increase in the achieved fault coverage with respect to the popular solution of observing the final content of the memory.