Impact of transistor technology on power savings in monolithic 3D ICs

In this paper, we discuss the impact of transistor technology on the power savings in monolithic 3D ICs over traditional 2D ICs. Our results are based on gate-level 3D IC partitioning and full RTL to GDSII design and analysis of a Low Density Parity Check (LDPC) benchmark circuit block with use of two different silicon validated foundry technologies. These two technologies have the same nominal operating voltage, but differ in terms of device performance, power, and gate capacitance. Our results show that monolithic 3D IC provides 37.5% more power savings for the technology with lower device power and input capacitance compared to that of a high power device technology.