A Reference-Free Capacitive-Discharging Oscillator Architecture Consuming 44.4 pW/75.6 nW at 2.8 Hz/6.4 kHz

This paper presents a capacitive-discharging oscillator architecture that achieves ultra-low-power operation without a temperature-stabilized reference generator by directly relying on the RC time constants of capacitors discharging across passively-temperature-stabilized resistive elements. The architecture operates by pre-charging two capacitors to the supply voltage, and then discharging one of the capacitors through a resistive path, while the other capacitor charge-shares with a third capacitor in order to generate a reference potential for comparison to flip phases. The architecture is demonstrated with two fully-integrated implementations in two different process technologies: 250 nm and 65 nm. The 250 nm implementation employs poly resistors, operates at 6.4 kHz, consumes 75.6 nW, and achieves a temperature stability of 0.74% (148 ppm/°C) from 20°C to 80°C when measured over five samples. The 65 nm implementation employs gate-leakage resistors, operates at 2.8 Hz, consumes 44.4 pW, and achieves a temperature stability of 1260 ppm/°C across a temperature range of -40°C to 60°C over five samples. The two implementations demonstrate low-cost, low-power, and stable timing solutions at Hz-to-kHz-range frequencies for next-generation Internet-of-Things sensors.