Test method and scheme for low-power validation in modern SOC integrated circuits

Test Mode power can be 5X higher than functional power in GPUs, while the power grid is designed only for worst-case functional toggle. The large simultaneous switching noise induced on the power rails during at-speed capture testing is constrained by means of hardware solution. To determine the best low power mode for ATPG, we propose novel techniques to: estimate global peak current (di), determine local droop trend and validate and further optimize chosen power settings with exhaustive post-silicon power mode tuning. During Power Optimization (PO) phase, the measured clock frequency (fclk) and Vdroop are analyzed on every pattern and test coverage and pattern count are optimized for the production pattern set. We share correlation results and Power Supply Noise (PSN) distribution for the production pattern set on recent 28-nm GPUs.