Process variation oriented delay testing of SRAMs

With continuing technology scaling, process variation is increasing and becoming an important cause of memory failure [1]. Most previous memory tests that were developed for delay faults, including GALPAT [2][3][4] and WCGD [3], focus on defects. In this paper we show that a different test strategy is necessary for process variation-induced delay faults (VIDFs) because variations are widespread. In particular, we determine that address dependent variation-induced failure mechanisms are likely to escape previous memory tests. We then propose a general approach to cover VIDFs in various versions of SRAM designs. We use our new method to generate O(n) tests and use extensive simulations to demonstrate that our new tests achieve nearly perfect coverage of VIDFs for different versions of SRAM design. Then we efficiently integrate our new tests for variations with tests for delay defects and clearly demonstrate the efficiency and effectiveness of our new combined memory tests compared to previously known memory tests for delay faults.