A Family of Ripple Estimation–Cancellation Methods Based on Switched-Resistor Circuits and Their Application in Fast-Response PFC Preregulator

Power-factor-correction (PFC) preregulator commonly suffers from slow dynamic response due to the need to operate with small closed-loop bandwidth for realizing low total harmonic distortion of input current. Ripple cancellation is one of the widely adopted strategies to achieve high power factor and fast dynamic response simultaneously. The main idea is to eliminate the double-line frequency component in the sampled output voltage by means of subtracting a replica of the output voltage ripple from the sampled output voltage. In this paper, a systematic derivation and analysis of the main figures of merit of PFC preregulator incorporating ripple cancellation is presented. Based on the equations obtained, three variants of a family of ripple cancellation methods based on switched-resistor circuits are proposed. The performances of these methods are experimentally investigated and compared by implementing them in a 200-W average-current-mode-controlled boost PFC preregulator. By comparing the measured figures of merit, it is shown that near-perfect ripple cancellation is achievable when the amplitude and phase angle of the sampled output voltage ripple are estimated independently, whereas a more cost-effective solution is provided by another approach that tracks the ripple amplitude only at the expense of decreased power factor and increased total harmonic distortion.