Statistical analysis and modeling of Random Telegraph Noise based on gate delay variation measurement

We propose a characterization and modeling methodology for Random Telegraph Noise (RTN) induced ΔVth variation based on gate delay variation measurement. We characterize the total amount of ΔVth and model its scaling effect. A topology-reconfigurable ring oscillator (RO) is used to obtain gate delay variations between inverter stages. The devices under test are operated at near- or sub-threshold region to characterize RTN at low supply voltage. Measurement and characterization results from a 65 nm test chip show that lognormal distribution based modeling represents RTN-induced ΔVth variability precisely. We extract the model parameters and evaluate the gate size dependency of these parameters. It is found that μl of the lognormal distribution, lnN(μl, σl2), does not have specific gate size dependency. Whereas, σ shows a W−a dependency to gate size rather than the commonly assumed W−1 dependency, where a is evaluated to be less than 0.5. The proposed comprehensive statistical model and its parameter dependency is suitable for performance analysis of circuits where transistors of different gate sizes are used.