A power consumption and area improved design of IIR decimation filters via MDT

This manuscript provides a novel method to improve occupied area, speed and power consumption of Infinite Impulse Response (IIR) decimation filter. The filter is design using proposed Merged Delay Transformed (MDT). First, mathematical calculation is performed and then applied effectively to first- and second-order IIR filters. The performance of the proposed design is compared with the exiting polyphase Finite Impulse Response (FIR) decimation filter and cascaded IIR decimation filter. The proposed method not only effective in term of reduction of area, power consumption, but also establishes better stability for coefficient quantization. Number of Multiplication involved in computing is reduced by 45.4% as compared to traditional IIR filters. The performance of the proposed method is checked through Matlab simulation and then implemented on FPGA Spartan-3 Kit using Xilinx tool.