Notice of Violation of IEEE Publication Principles: An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors

Notice of Violation of IEEE Publication Principles

"An Energy-efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors"
by Salman Onsori, Arghavan Asad, Kaamran Raahemifar
in the IEEE Transactions on Emerging Topics in Computing, (Early Access), May 2016

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper contains text and a figure copied from the paper cited below. The original content was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.

"Retention Time Aware STT-RAM based L1-Cache in Multi-Core Processors"
by Bahar Asgari, Mahdi Fazeli, Ahmad Patooghy, Mostafa Kajouian; Farzaneh Rabiee
submitted to Elsevier Microprocessors and Microsystems, November 2015


Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era causes a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we present a convex optimization model to design a 3D stacked hybrid memory architecture in order to minimize the future embedded systems energy consumption in the dark silicon era. This proposed approach satisfies endurance constraint in order to design a reliable memory system. Our convex model optimizes numbers and placement of eDRAM and STT-RAM memory banks on the memory layer to exploit the advantages of both technologies in future eCMPs. Energy consumption, the main challenge in the dark silicon era, is represented as a major target in this work and it is minimized by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor. Experimental results show that in comparison with the Baseline memory design, the proposed architecture improves the energy consumption and performance of the 3D CMP on average about 61.33% and 9% respectively.