Characterization and performance prediction for integral capacitors in low temperature co-fired ceramic technology

This paper addresses the electrical characterization of integral capacitors in low temperature co-fired ceramic (LTCC). The technology also includes integrated resistors and inductors. It first discusses the geometry and fabrication of the capacitor technology, which uses a novel insert method in LTCC substrates. The structures of 300 special test vehicles made to analyze the technique are described. The samples include components in the range 140 pF to 9.6 nF, and single-layer and two-layer integral formats; structure fabrication capability is currently 7.8 nF/cm/sup 2/. Test vehicle variants, fabricated to analyze the effects of processing parameters such as lamination pressure, are discussed. Measurement systems, which were built to electrically characterize the integral capacitors, are described. The results of the analyzes are summarized with regard to the individual and combined impact of applied frequency, temperature, and DC voltage parameters. The effects of lamination pressure, capacitor size, and the number of dielectric layers are also evaluated. The paper then discusses the development of predictive functions for the induced electrical performance variations in the capacitors, functions that are necessary to enable designers to properly develop circuits for applications in various operating environments. The results of an analysis of the geometry of the capacitors are presented, and are employed by electrical models made using analytical methods, boundary element methods (BEM), and finite element methods (FEM). The models are a requirement for process engineers in optimizing the capacitor fabrication techniques, and for design engineers as means of defining the correct component geometries for their circuits.