A 1.2 V, 0.1 /spl mu/m gate length CMOS technology: design and process issues

CMOS technology is being scaled to sub-0.1 /spl mu/m gate length and to power supply (V/sub dd/) of 1.2 V for applications of high density at lower active power than achievable with a 1.5 V-1.8 V CMOS. Many challenges are observed at this technology node including choice of gate dielectric for applications with sub-2.5 nm physical SiO/sub 2/ gate dielectric (or electrical equivalent), and maintaining roadmap performance at 1.2 V, which will require an increase in maximum off current. In this work, the nitrided gate dielectric is formed by Remote-Plasma Nitridation (RPN) of an initial thick and thus, manufacturable, physical SiO/sub 2/ layer /spl sim/3.0 nm, to achieve a final effective physical dielectric thickness /spl les/2.5 nm. In this work, for an effective t/sub ox/(acc)=3.0 nm (corresponding to /spl sim/2.5 nm effective physical Si0/sub 2/ dielectric), nMOS and pMOS nominal I/sub drive/ is 532-55 /spl mu//spl Aring///spl mu/m and 230-240 /spl mu//spl Aring///spl mu/m, respectively, at 1.2 V, with max. I/sub off/=5-10 nA//spl mu/m, With an increase in maximum I/sub off/ from 1 nA//spl mu/m (previous work) to e.g. 5 nA//spl mu/m, the 1.2 V FOM is within 3% of the target figure-of-merit specification. Nonetheless, for scaled 1.2 V technology, the effective physical gate dielectric thickness will be required to be reduced to <2.5 nm for sufficient I/sub drive/ to meet high performance requirements.