Accurate characterization of electron and hole inversion-layer capacitance and its impact on low voltage operation of scaled MOSFETs

The influence of inversion-layer capacitance (C/sub inv/) on supply voltage (V/sub dd/) of n- and p-MOSFETs is quantitatively examined. Hole C/sub inv/ is experimentally evaluated in addition to electron C/sub inv/. It is found that the degradation of gate capacitance for holes due to C/sub inv/, is more severe than that for electrons. Self-consistent calculation under a simple valence band model represents the experimental hole C/sub inv/, quite well. It is demonstrated that additional band bending of a Si substrate due to C/sub inv/ becomes a dominant factor to limit the lowering of V/sub dd/ for CMOS with ultra-thin gate oxides. The operation at V/sub dd/ lower than 0.6 V is quite difficult even with effective T/sub OX/ less than 1 nm.