Upstream data analytics to optimize system test

Shrinking semiconductor feature sizes are giving rise to subtle defects that cause marginal circuit behavior rather than hard failures. As test and system modes of operation diverge in complex devices, marginal defects can escape production test but trigger end-system failures. Thus system-level testing (SLT) becomes imperative. But SLT adds extra cost and limits volume throughput. This paper describes upstream test data analytics to optimize SLT deployment. At the wafer level, local region yield data can selectively subject at-risk dies to SLT. Another scheme applies on-chip-clocked scan patterns under non-destructive stress conditions to obtain device features indicative of local parametric quality. Features bearing statistical outliers are then extracted as signatures of marginality to guide SLT decisions. Results from SoC products show the potential of adaptive SLT.