A study of photo-resist strip at dummy poly gate removal process

As CMOS process is advancing towards the high-k/metal gate (HK/MG) technology, dummy poly gate removal (DPGR) process, one of key steps in gate-last technology, poses the challenge for its multiple-film related etching process. Its subsequent photo-resist (PR) strip process is also very difficult due to rigorous process requirements and rather limited wet clean resource. The DPGR process in this work includes two separate DPGR processes for n/p-MOS structures. In the 1st DPGR PR strip process, PR strip capability significantly improves with higher power, higher temperature and higher hydrogen flow-rate. Unlike its PR strip process, post etch treatment (PET) with lower temperature is proven helpful for the 2nd DPGR PR strip. In addition, both bias temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) have been enhanced with the optimized PR strip processes.