The impact of metal hard-mask AIO etch on BEOL electrical performance

In advanced CMOS technology nodes with Cu/low-k interconnect, as Cu line CD continues being scaled, the back-end-of-line (BEOL) electrical performance significantly impacts the chip operation speed by total RC (Resistance and Capacitance) delay. The resistance includes metal sheet resistance (RS) and via contact resistance (RC), while the capacitance includes inter metal and intra metal capacitance. Metal sheet resistance is always coupled with intra metal capacitance, so trench CD and profile dominate both metal resistance and intra metal capacitance if low-k damage is well controlled. The trench CD and profile associated with lower RC delay are proposed. If gap filling capability is considered, tapered trench profile is preferred and then metal HM CD and film thickness need be optimized to meet the RC delay target. The contact resistance of via is dominated by via contact area. Via bottom CD and trench top CD decide the contact area together and both of them are critical for KV RC reduction. Via chamfer profile effect on via resistance is insignificant. Partial via etch depth plays totally different role in KV RC on two different kinds of film stack. The mechanism of this phenomenon is addressed. Such complex correlation between via and trench is investigated in this paper by means of electrical performance testing, meanwhile the impact of AIO etch on BEOL electrical performance is revealed correspondingly.