Floating gate etch profile control for NAND flash memory

As the density of flash memory devices, especially NAND flash, increases considerably in the past decade [1, 2]. Consequently, the feature size of cells, or the pitch critical dimension (CD), shrinks remarkably and, as a result, the aspect ratio (AR) of the gate, including control gate (CG) and floating gate (FG), is going much higher than before. Such AR value could be up to 6:1 or even higher, which may greatly impact the FG profile during the dry etch process. Some issues, as word-line (WL) bridge, result from the problematic profile. In this contribution, we investigate several parameters such as pressure, plasma source power (TCP), RF bias-voltage, plasma etcher gas, etc., all of which aim to achieve vertical FG profile. The result demonstrates the fact that the approach to the vertical profile is correlated to the pressure and the ratio of TCP to bias-voltage during such high-AR dry-etch process: high pressure and low source power/bias voltage ratio help to achieve the vertical profile. The circuit probe (CP) test shows that such vertical FG profile benefits the overall yield.