A 0.996mW 10GHz slicer with 20mV input resolution in 65nm CMOS

In high-speed serial communication interface circuits, a high-performance slicer is essential. This paper presents an improved slicer based on SA/FF (Sense Amplifier/Flip Flop) and extracts the sample function of whole circuit system. The results show that the proposed configuration can achieve a regeneration gain of 61.8dB and a -3dB bandwidth of 10GHz. The power consumption of the new structure is 0.996mW at 10GHz, and the input resolution is 20mV under this clock frequency. Besides, the delay of slicer is independent on the variation of common mode voltage.