A novel electrical-mechanical simulation flow to predict stress-induced circuit shifts

In this paper we present an approach to provide insight in electrical parameter shifts due to mechanical stress by means of mechanical modelling through FEA. A fast assessment of the expected parameter shift as a function of location and current direction with respect to stressors can directly be made using the FEA tool. Additionally the results can be exported for usage in electrical circuit simulation tools such as Cadence ADE. The link with such tools enables a more detailed investigation into the effects of stress on parts of the circuit and potential amplification of small shifts. Simulated results based on a test case involving solder bump induced stress are compared with measurements on dedicated high resolution test chips. The measurements show a good correlation with the simulation results, both qualitatively and quantitatively.