Wafer Level Chip Scale Packaging: Thermo-mechanical failure modes, challenges & guidelines

WLCSP (Wafer Level Chip Scale Packaging) is used to enable low-cost manufacturing and a high performance featuring low I/O density. Such a solution provides a solder interconnection directly between the die and motherboard. This paper aims at presenting the specificities of this new assembly by describing the most common thermo-mechanical failures encountered and by proposing some containment solutions and ways of improvement. Despite its advantages, this solution raises particular thermo-mechanical failures. Cracking of passivation or under layers, humidity penetration and/or delamination from the die edge are some of the main issues generally observed. Moreover, we need to pay extra attention to the die edge since this region is particularly sensitive. Indeed, for Fan-In configuration, the die is exposed to the atmosphere (no molding compound surrounding the die), leading to chemical contamination and cracks. Numerous causes are involved: e.g. non-optimized sawing process and weakness of the seal ring structure (i.e. metal pattern surrounding the die and providing mechanical and chemical shields). Furthermore, due to the bump and passivation layer proximities, some interactions may exist with the BEoL stack itself. FEM (Finite Element Method) is carried out, with a particular focus on the Fan-In package. Typical stress fields are provided, giving clues on WLCSP package specificities to mitigate mechanical hazard. Then, following the previously depicted failures, both the die and the passivation edges are comprehensively studied. It is shown that a stress peak is induced by the passivation edge, providing requirements on the deposit strategy (direct or pyramidal) and the edge location. Additionally, it is shown that the residual stress and the thickness of the BEoL passivation layer have also to be reduced and increased respectively.