A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity

An SRAM cell is proposed, in which additional capacitance is formed between the two local interconnects which are used for cross couple wiring. This novel cell with stacked cross couple (SCC) has an advantage in reducing the cell area to 80% of that of the conventional SRAM cell. Furthermore, the capacitor area can be enlarged to 40% of the cell area which enables one to adopt thick capacitor insulator. Reduction in capacitor leakage current by using plasma SiN with low Si-H concentration, and the device performances are also discussed.